EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
EDN

Algorithms go from floating- to fixed-point

Migrating signal-processing algorithms from floating- to fixed-point is often necessary to meet various design constraints, including real-time performance, cost and power dissipation. The migration ...
TechRepublic

A High Speed Binary Floating Point Multiplier Using Vedic Algorithm

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high ...
Semiconductor Engineering

Achieving Numerical Precision And Design Customization With Flexible Floating-Point IP

As defined by the IEEE 754 standard, floating-point values are represented in three fields: a significand or mantissa, a sign bit for the significand and an exponent field. The exponent is a biased ...