IEEE

Design and Implementation of Single Precision Floating-point Arithmetic Logic Unit for RISC Processor on FPGA

Abstract: The main purpose of conducting this research is to design and implement a single precision floating-point arithmetic logic unit (ALU) that considered as a part of the math coprocessor. The ...
GitHub

Rethinking Network Design and Local Geometry in Point Cloud: A Simple Residual MLP Framework （ICLR 2022）

Overview of one stage in PointMLP. Given an input point cloud, PointMLP progressively extracts local features using residual point MLP blocks. In each stage, we first transform the local point using a ...
IEEE

SecFloat: Accurate Floating-Point meets Secure 2-Party Computation

Abstract: We build a library SecFloat for secure 2-party computation (2PC) of 32-bit single-precision floating-point operations and math functions. The existing functionalities used in cryptographic ...
GitHub

FPnew - New Floating-Point Unit with Transprecision Capabilities

The FPU is a parametric design that allows generating FP hardware units for various use cases. Even though mainly designed for use in RISC-V processors, the FPU or its sub-blocks can easily be ...