IEEE

A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration

Abstract: This article presents a 7-bit, 1.15-GS/s, 2.6-bit/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that incorporates a comparator decision skip ...
IEEE

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm

Abstract: In this article, we introduce a new dynamically biased ring amplifier that is tolerant to mismatch and PVT variation without requiring bias calibration, and we verify it in a 12-bit 400-MS/s ...