Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

For a useful primer on circuit design, see Optimize your DSPs for power and performance. To learn how power and performance vary with voltage and temperature, see Push performance and power beyond the ...

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

Technology developed for driving synchronous FETs in flyback topologies can be directly applied in LLC topologies. This technology offers significant gains in efficiency for applications with low ...

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...

Power supplies that use diodes to rectify an ac voltage to obtain a dc voltage must deal with inherent inefficiencies. A standard diode or ultra-fast diode can have a 1-V forward voltage or higher at ...

Given the growing importance and impact of portable, battery-operated devices in today’s society, it’s easy to understand why power consumption has become such a critical factor in IC design. But it’s ...

Combining the advantages of permanent magnet and induction motors, new synchronous reluctance motors (SynRM) offer potentially breakthrough technology for variable speed drive (VSD) and motor packages ...