EDN

Tools accurately simulate noise in mixed-signal ASICs

In some capacitive-sensor applications, the ability to obtain noise levels as low as 10 aF (atofarad) rms in capacitive-sensor-interface ASICs is critical to high performance. To achieve such low ...
Electronic Design

Noise Reduction is Crucial to Mixed-Signal ASIC Design Success (Part 2)

Separating the power/ground connections used for the analog sections from those used for the digital areas will improve the isolation of the power supplies. Adding external/internal filtering should ...
Electronic Design

Ultra-Low-Power, Ultra-Low-Noise ASIC Breakthroughs Enable New MEMS Sensors

Often, a technological breakthrough can lead to new products and even new applications that had previously been considered fantasy. Developments in low-power, low-noise readout ASICs could open new ...
Design-Reuse

Structured ASIC Based SoC Design

Complex System-on-Chip (SoC) designs are fast becoming commonplace in today’s applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market (TTM), ...
Design-Reuse

Analogue Insight Safe Announces AISAFE Digital Noise Source IP for Scalable Performance Hardware Entropy Sources in ASICs

Metastability-based physical noise source with digitization designed to support NIST SP800-G0B and AIS 20/31 entropy-sources. The design leverages metastability to produce high data rate random bits ...